From 11f2eb8d35631194df2d91e6f9bdfa65a7618e90 Mon Sep 17 00:00:00 2001
From: TQ Hirsch <thequux@thequux.com>
Date: Tue, 19 Sep 2023 23:35:32 +0200
Subject: [PATCH] Now gets through most of EKBA; fails test of T bit

---
 src/main/kotlin/com/thequux/mcpdp/core/CPU.kt | 29 ++++++++++---------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
index e9a0623..02e8aa2 100644
--- a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
+++ b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
@@ -43,14 +43,15 @@ class CPU(val mbus: MemBus) {
     var psw: UShort
         get() {
             var res = 0
-            if (C) res = res or 0x0001
-            if (V) res = res or 0x0002
-            if (Z) res = res or 0x0004
-            if (N) res = res or 0x0008
-            if (T) res = res or 0x0010
+            if (C) { res = res or 0x0001 }
+            if (V) { res = res or 0x0002 }
+            if (Z) { res = res or 0x0004 }
+            if (N) { res = res or 0x0008 }
+            if (T) { res = res or 0x0010 }
             res = res or (psw_priority shl 5)
             res = res or (cur_mode shl 14) or (prv_mode shl 12)
             res = res or (registerSet shl 11)
+            logger.debug("PSW: ${res.toString(16)}")
             return res.toUShort()
         }
         set(value) {
@@ -342,8 +343,8 @@ class CPU(val mbus: MemBus) {
                         N = res bit 15
                         Z = res == 0.toUShort()
                         V = res == 0x8000.toUShort()
-                        debugFlags()
-                        logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${src.toString(16)}")
+//                        debugFlags()
+//                        logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${src.toString(16)}")
 
                     } // INC
                     3 -> { // DEC
@@ -593,6 +594,7 @@ class CPU(val mbus: MemBus) {
                 }
             } // MOV
             0x2000 -> { // CMP
+
                 val src = op_loadw(opc_src(opcode))
                 val src2 = op_loadw(opc_dst(opcode))
                 val res = (src - src2) and 0xFFFFu
@@ -608,8 +610,8 @@ class CPU(val mbus: MemBus) {
                 N = res bit 15
                 Z = res == 0u.toUShort()
                 V = false
-                logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${op_loadw(src).toString(16)}")
-                debugFlags()
+//                logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${op_loadw(src).toString(16)}")
+//                debugFlags()
             } // BIT
             0x4000 -> { // BIC
                 val src = opc_src(opcode)
@@ -641,7 +643,10 @@ class CPU(val mbus: MemBus) {
                 Z = resw == 0.toUShort()
                 val src_sign = srcv and 0x8000u
                 V = (src_sign == dstv and 0x8000u) && (src_sign != resw and 0x8000u)
-                C = (resw >= 0x10000u)
+                C = (res >= 0x10000u)
+//                logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${srcv.toString(16)}, DST: ${dstv.toString(16)}")
+//                debugFlags()
+
             } // ADD
             0x7000 -> when (opcode shr 9 and 0x7) {
                 0 -> { // MUL
@@ -757,8 +762,6 @@ class CPU(val mbus: MemBus) {
                 N = dstv bit 7
                 Z = dstv == 0.toUByte()
                 V = false
-                logger.debug("RV: ${dst.toString(16)} RES: ${dstw.toString(16)}, SRC: ${dstv.toString(16)}")
-                debugFlags()
 
             } // MOVB
             0xA000 -> { // CMPB
@@ -806,7 +809,7 @@ class CPU(val mbus: MemBus) {
                 N = res < 0
                 Z = res == 0
                 V = ((srcv bit 31) xor (dstv bit 15)) and ((srcv bit 15) == (res bit 31))
-                C = (dst.toInt() + src.inv().inc().toInt()) < 0x1_0000
+                C = (dst.toInt() + src.inv().inc().toInt()) >= 0x1_0000
             } // SUB
         }
     }