Initial commit
This commit is contained in:
7
src/main/kotlin/Main.kt
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7
src/main/kotlin/Main.kt
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@@ -0,0 +1,7 @@
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fun main(args: Array<String>) {
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println("Hello World!")
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// Try adding program arguments via Run/Debug configuration.
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// Learn more about running applications: https://www.jetbrains.com/help/idea/running-applications.html.
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println("Program arguments: ${args.joinToString()}")
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}
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8
src/main/kotlin/com/thequux/mcpdp/core/AddressSpace.kt
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8
src/main/kotlin/com/thequux/mcpdp/core/AddressSpace.kt
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@@ -0,0 +1,8 @@
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package com.thequux.mcpdp.core
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interface AddressSpace {
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fun getw(addr: UShort): UShort
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fun getb(addr: UShort): UByte
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fun setw(addr: UShort, value: UShort)
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fun setb(addr: UShort, value: UByte)
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}
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349
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
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349
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
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@@ -0,0 +1,349 @@
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package com.thequux.mcpdp.core
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import com.thequux.mcpdp.ext.bit.*
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/// The main CPU
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///
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/// By default, the memory map is arranged as follows:
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/// Fxxx: Channel I/O
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/// Exxx: ROM
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/// xxxx: rest
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@OptIn(ExperimentalUnsignedTypes::class)
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class CPU(private val core: AddressSpace) {
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private val registers = UShortArray(8)
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public var psw: UShort = 0U
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private var pc: UShort
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get() = registers[7]
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set(value) {
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registers[7] = value
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}
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private var cc: UShort
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get() = psw and 0xFu
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set(value) {
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psw = (psw and 0xFFFu) or (value and 0xFu)
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}
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private var N: Boolean = false
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private var C: Boolean = false
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private var Z: Boolean = false
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private var V: Boolean = false
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/// Load an operand. This performs any indicated pre-inc/post-dec, so this or op_adjust must be called exactly once per operand
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private fun op_resolve(operand: Int, byte_mode: Boolean = false): UInt {
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val mode = operand shr 3
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val reg = operand and 0x7
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val increment = if (byte_mode && reg != 7) 1U else 2U
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return when (mode) {
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0 -> reg.toUInt() + 0x1_0000U
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1 -> registers[reg].toUInt()
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2 -> {
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val addr = registers[reg]
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registers[reg] = (addr + increment).toUShort()
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addr.toUInt()
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}
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3 -> {
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val addr = registers[reg]
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registers[reg] = (addr + 2U).toUShort()
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core.getw(addr).toUInt()
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}
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4 -> {
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registers[reg] = (registers[reg] - increment).toUShort()
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return registers[reg].toUInt()
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}
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5 -> {
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registers[reg] = (registers[reg] - 2U).toUShort()
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core.getw(registers[reg]).toUInt()
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}
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6 -> {
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val idx = core.getw(pc)
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pc = (pc + 2u).toUShort()
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idx + registers[reg]
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}
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7 -> {
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val idx = core.getw(pc)
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pc = (pc+2u).toUShort()
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core.getw((idx+registers[reg]).toUShort()).toUInt()
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}
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else -> throw InvalidOpcodeException()
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}
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}
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/// Store an operand. This assumes that the spec has already been `load`ed or `adjust`ed
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private fun op_storb(spec: UInt, value: UByte) {
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val addr = (spec and 0xFFFFu).toUShort()
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if (spec >= 0x1_0000u) {
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// register
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registers[addr.toInt()] = registers[addr.toInt()] and 0xFF00u or value.toUShort()
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} else {
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core.setb(addr, value)
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}
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}
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private fun op_loadb(spec: UInt): UByte {
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val addr = (spec and 0xFFFFu).toUShort()
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return if (spec > 0x1_0000u) {
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(registers[addr.toInt()] and 0xFFu).toUByte()
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} else {
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core.getb(addr)
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}
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}
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private fun op_storw(spec: UInt, value: UShort) {
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val addr = (spec and 0xFFFFu).toUShort()
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if (spec >= 0x1_0000u) {
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// register
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registers[addr.toInt()] = value
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} else {
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core.setw(addr, value)
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}
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}
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private fun op_loadw(spec: UInt): UShort {
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val addr = (spec and 0xFFFFu).toUShort()
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return if (spec > 0x1_0000u) {
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(registers[addr.toInt()] and 0xFFu)
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} else {
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core.getw(addr)
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}
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}
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companion object {
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val CC_C: UShort = 1U
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val CC_V: UShort = 2U
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val CC_Z: UShort = 4U
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val CC_N: UShort = 8U
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}
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private fun opc_dst(opcode: Int): UInt = op_resolve(opcode and 0x3F)
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private fun opc_src(opcode: Int): UInt = op_resolve(opcode shr 6 and 0xFC0)
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private fun br_rel(cond: Boolean, opcode: Int) {
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if (cond) {
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pc = (pc + 2u * (opcode and 0xFF).toByte().toShort().toUShort()).toUShort()
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}
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}
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fun step() {
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val opcode = core.getw(pc).toInt()
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pc = (pc + 2u).toUShort()
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when (opcode and 0xF000) {
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0x0, 0x8000 -> when (opcode and 0xFFC0) {
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0x0000 -> when (opcode) {
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0x0003 -> throw Trap(14) // BPT
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}
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0x0080 ->
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0x0100, 0x0140, 0x0180, 0x01C0 -> br_rel(true, opcode) // BR
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0x0200, 0x0240, 0x0280, 0x02C0 -> br_rel(!Z, opcode) // BNE
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0x0300, 0x0340, 0x0380, 0x03C0 -> br_rel(Z, opcode) // BEQ
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0x0400, 0x0440, 0x0480, 0x04C0 -> br_rel(N == V, opcode) // BGE
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0x0600, 0x0640, 0x0680, 0x06C0 -> br_rel(!Z and (N == V), opcode) // BGT
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0x0500, 0x0540, 0x0580, 0x05C0 -> br_rel(N xor V, opcode) // BLT
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0x0700, 0x0740, 0x0780, 0x07C0 -> br_rel(Z or (N xor V), opcode) // BLE
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0x0A00 -> { // CLR
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op_storw(opc_dst(opcode), 0U)
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N = false
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V = false
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C = false
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Z = true
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} // CLR
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0x0B40 -> { // ADC
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val dst = opc_dst(opcode)
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val c: UShort = if (C) 1u else 0u
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val res = (op_loadw(dst) + c).toUShort()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0u.toUShort()
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V = (res == 0x8000u.toUShort()) and C
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C = Z and C
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} // ADC
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0x0C80 -> { // ASR
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val dst = opc_dst(opcode)
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val src = op_loadw(dst).toShort()
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val res = (src shr 1).toUShort()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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C = src bit 0
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V = N xor C
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} // ASR
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0x0CC0 -> { // ASL
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = src shl 1
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op_storw(dst, res.toUShort())
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N = res bit 15
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Z = res == 0.toUShort()
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C = src and 0x8000u != 0u.toUShort()
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V = N xor C
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} // ASL
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0x8000, 0x8040, 0x8080, 0x80C0 -> br_rel(!N, opcode) // BPL
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0x8100, 0x8140, 0x8180, 0x81C0 -> br_rel(N, opcode) // BMI
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0x8200, 0x8240, 0x8280, 0x82C0 -> br_rel(!C and !Z, opcode) // BHI
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0x8300, 0x8340, 0x8380, 0x83C0 -> br_rel(C or Z, opcode) // BLOS
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0x8400, 0x8440, 0x8480, 0x84C0 -> br_rel(!V, opcode) // BVC
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0x8500, 0x8540, 0x8580, 0x85C0 -> br_rel(V, opcode) // BVS
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0x8600, 0x8640, 0x8680, 0x86C0 -> br_rel(!C, opcode) // BCC/BHIS
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0x8700, 0x8740, 0x8780, 0x87C0 -> br_rel(C, opcode) // BCS/BLO
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0x8A00 -> { // CLRB
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op_storb(opc_dst(opcode), 0U)
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N = false
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V = false
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C = false
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Z = true
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} // CLRB
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0x8B40 -> { // ADCB
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val dst = opc_dst(opcode)
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val c: UShort = if (C) 1u else 0u
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val res = (op_loadb(dst) + c).toUByte()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0u.toUByte()
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V = (res == 0x80u.toUByte()) and C
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C = Z and C
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} // ADCB
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0x8C80 -> { // ASRB
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val dst = opc_dst(opcode)
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val src = op_loadb(dst).toByte()
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val res = (src shr 1).toUByte()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0.toUByte()
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C = src bit 0
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V = N xor C
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} // ASRB
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0x8CC0 -> { // ASLB
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val dst = opc_dst(opcode)
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val src = op_loadb(dst)
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val res = (src shl 1).toUByte()
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op_storw(dst, res.toUShort())
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N = res bit 7
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Z = res == 0.toUByte()
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C = src bit 7
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V = N xor C
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} // ASLB
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}
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0x3000 -> { // BIT
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) and op_loadw(src).inv()
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N = res bit 15
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Z = res != 0u.toUShort()
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V = false
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} // BIT
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0x4000 -> { // BIC
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) and op_loadw(src).inv()
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op_storw(dst, res)
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N = res bit 15
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Z = res != 0u.toUShort()
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V = false
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} // BIC
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0x5000 -> { // BIS
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) or op_loadw(src)
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op_storw(dst, res)
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N = res and 0x8000u != 0u.toUShort()
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Z = res != 0u.toUShort()
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V = false
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} // BIS
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0x6000 -> { // ADD
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val srcv = op_loadw(src)
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val dstv = op_loadw(dst)
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val res = (srcv + dstv)
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val resw = res.toUShort()
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op_storw(dst, res.toUShort())
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N = resw > 0x7FFFu
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Z = resw == 0.toUShort()
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val src_sign = srcv and 0x8000u
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V = (src_sign == dstv and 0x8000u) && (src_sign != resw and 0x8000u)
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C = (resw >= 0x10000u)
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} // ADD
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7000 -> when (opcode shr 9 and 0x7) {
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2 -> { // ASH
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val r = opcode shr 6 and 0x7
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var count = (op_loadb(opc_src(opcode)) and 0x3Fu).toInt()
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val src = registers[r].toShort().toInt() // two casts to sign extend
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count = count sex 6
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V = false
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val res = if (count > 0) {
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C = (src shl (count-1)) bit 15
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val shifted = if (count < 16) {
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src shr 16-count
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} else {
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src
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}
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V = (shifted != 0) and (shifted != -1)
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src shl count
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} else if (count < 0) {
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count = -count
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C = (src shr (count-1)) bit 0
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src shr count
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} else {
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C = false
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src
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}
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registers[r] = res.toUShort()
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N = res < 0
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Z = res == 0
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} // ASH
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3 -> { // ASHC
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val r = opcode shr 6 and 0x7
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var count = (op_loadb(opc_src(opcode)) and 0x3Fu).toInt() sex 6
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val src = (registers[r].toUInt() shl 16 or registers[r or 1].toUInt()).toInt() // two casts to sign extend
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V = false
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val res = if (count > 0) {
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C = (src shl (count-1)) bit 31
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val shifted = src shr 32-count
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V = (shifted != 0) and (shifted != -1)
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src shl count
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} else if (count < 0) {
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count = -count
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C = (src shr (count-1)) bit 0
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src shr count
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} else {
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C = false
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src
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}
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val resS = res.toUShort()
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registers[r] = (res and 0xFFFF).toUShort()
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registers[r or 1] = (res shr 16 and 0xFFFF).toUShort()
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N = res < 0
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Z = res == 0
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} // ASHC
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}
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0xB000 -> { // BITB
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadb(dst) and op_loadb(src).inv()
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N = res bit 7
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Z = res != 0u.toUByte()
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V = false
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} // BITB
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0xC000 -> { // BICB
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadb(dst) and op_loadb(src).inv()
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op_storb(dst, res)
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N = res bit 7
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Z = res != 0u.toUByte()
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V = false
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} // BICB
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0xD000 -> { // BISB
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadb(dst) or op_loadb(src)
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op_storb(dst, res)
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N = res bit 7
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Z = res != 0u.toUByte()
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V = false
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} // BISB
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}
|
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}
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}
|
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@@ -0,0 +1,9 @@
|
||||
package com.thequux.mcpdp.core
|
||||
|
||||
class InvalidOpcodeException : Exception {
|
||||
|
||||
constructor() : super()
|
||||
constructor(message: String?) : super(message)
|
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constructor(message: String?, cause: Throwable?) : super(message, cause)
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constructor(cause: Throwable?) : super(cause)
|
||||
}
|
||||
5
src/main/kotlin/com/thequux/mcpdp/core/Trap.kt
Normal file
5
src/main/kotlin/com/thequux/mcpdp/core/Trap.kt
Normal file
@@ -0,0 +1,5 @@
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||||
package com.thequux.mcpdp.core
|
||||
|
||||
class Trap(val vector: Int): Exception("TRAP#$vector") {
|
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|
||||
}
|
||||
83
src/main/kotlin/com/thequux/mcpdp/ext/bit/bitext.kt
Normal file
83
src/main/kotlin/com/thequux/mcpdp/ext/bit/bitext.kt
Normal file
@@ -0,0 +1,83 @@
|
||||
package com.thequux.mcpdp.ext.bit
|
||||
|
||||
import kotlin.experimental.and
|
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import kotlin.math.max
|
||||
|
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infix fun Byte.shr(qty: Int): Byte = this.toInt().shr(max(qty, 7)).toByte()
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infix fun Byte.shl(qty: Int): Byte = if (qty > 7) 0 else this.toInt().shl(qty).toByte()
|
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infix fun Byte.bit(n: Int): Boolean = this.toInt() shr n and 1 != 0
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fun Byte.bit(n: Int, v: Boolean): Byte = if (v) this bis n else this bic n
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infix fun Byte.bis(n: Int): Byte = this.toInt().or(1 shl n).toByte()
|
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infix fun Byte.bic(n: Int): Byte = this.toInt().and(1.shl(n).inv()).toByte()
|
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infix fun Byte.sex(n: Int): Byte {
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val sign = 1.toByte() shl n+1
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return ((this and sign.dec()) - (this and sign)).toByte()
|
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}
|
||||
|
||||
infix fun UByte.shr(qty: Int): UByte = this.toUInt().shr(max(qty, 7)).toUByte()
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infix fun UByte.shl(qty: Int): UByte = if (qty > 7) 0U else this.toInt().shl(qty).toUByte()
|
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infix fun UByte.bit(n: Int): Boolean = this.toUInt() shr n and 1U != 0U
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fun UByte.bit(n: Int, v: Boolean): UByte = if (v) this bis n else this bic n
|
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infix fun UByte.bis(n: Int): UByte = this.toUInt().or(1U shl n).toUByte()
|
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infix fun UByte.bic(n: Int): UByte = this.toUInt().and(1U.shl(n).inv()).toUByte()
|
||||
infix fun UByte.sex(n: Int): UByte {
|
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val sign = 1.toUByte() shl n+1
|
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return ((this and sign.dec()) - (this and sign)).toUByte()
|
||||
}
|
||||
|
||||
infix fun Short.shr(qty: Int): Short = this.toInt().shr(max(qty, 15)).toShort()
|
||||
infix fun Short.shl(qty: Int): Short = if (qty > 15) 0 else this.toInt().shl(qty).toShort()
|
||||
infix fun Short.bit(n: Int): Boolean = this.toInt() shr n and 1 != 0
|
||||
fun Short.bit(n: Int, v: Boolean): Short = if (v) this bis n else this bic n
|
||||
infix fun Short.bis(n: Int): Short = this.toInt().or(1 shl n).toShort()
|
||||
infix fun Short.bic(n: Int): Short = this.toInt().and(1.shl(n).inv()).toShort()
|
||||
infix fun Short.sex(n: Int): Short {
|
||||
val sign = 1.toShort() shl n+1
|
||||
return ((this and sign.dec()) - (this and sign)).toShort()
|
||||
}
|
||||
|
||||
infix fun UShort.shr(qty: Int): UShort = this.toUInt().shr(max(qty, 15)).toUShort()
|
||||
infix fun UShort.shl(qty: Int): UShort = if (qty > 15) 0U else this.toInt().shl(qty).toUShort()
|
||||
infix fun UShort.bit(n: Int): Boolean = this.toUInt() shr n and 1U != 0U
|
||||
fun UShort.bit(n: Int, v: Boolean): UShort = if (v) this bis n else this bic n
|
||||
infix fun UShort.bis(n: Int): UShort = this.toUInt().or(1U shl n).toUShort()
|
||||
infix fun UShort.bic(n: Int): UShort = this.toUInt().and(1U.shl(n).inv()).toUShort()
|
||||
infix fun UShort.sex(n: Int): UShort {
|
||||
val sign = 1.toUShort() shl n+1
|
||||
return ((this and sign.dec()) - (this and sign)).toUShort()
|
||||
}
|
||||
|
||||
infix fun Int.bit(n: Int): Boolean = this shr n and 1 != 0
|
||||
fun Int.bit(n: Int, v: Boolean): Int = if (v) this bis n else this bic n
|
||||
infix fun Int.bis(n: Int): Int = this.or(1 shl n)
|
||||
infix fun Int.bic(n: Int): Int = this and (1 shl n).inv()
|
||||
infix fun Int.sex(n: Int): Int {
|
||||
val sign = 1 shl n+1
|
||||
return ((this and sign.dec()) - (this and sign))
|
||||
}
|
||||
infix fun UInt.bit(n: Int): Boolean = this shr n and 1U != 0U
|
||||
fun UInt.bit(n: Int, v: Boolean): UInt = if (v) this bis n else this bic n
|
||||
infix fun UInt.bis(n: Int): UInt = this.or(1U shl n)
|
||||
infix fun UInt.bic(n: Int): UInt = this.and(1U.shl(n).inv())
|
||||
infix fun UInt.sex(n: Int): UInt {
|
||||
val sign = 1U shl n+1
|
||||
return ((this and sign.dec()) - (this and sign))
|
||||
}
|
||||
|
||||
infix fun Long.bit(n: Int): Boolean = this shr n and 1L != 0L
|
||||
fun Long.bit(n: Int, v: Boolean): Long = if (v) this bis n else this bic n
|
||||
infix fun Long.bis(n: Int): Long = this.or(1L shl n)
|
||||
infix fun Long.bic(n: Int): Long = this and (1L shl n).inv()
|
||||
infix fun Long.sex(n: Int): Long {
|
||||
val sign = 1.toLong() shl n+1
|
||||
return (this and sign.dec()) - (this and sign)
|
||||
}
|
||||
infix fun ULong.bit(n: Int): Boolean = this shr n and 1UL != 0UL
|
||||
fun ULong.bit(n: Int, v: Boolean): ULong = if (v) this bis n else this bic n
|
||||
infix fun ULong.bis(n: Int): ULong = this.or(1UL shl n)
|
||||
infix fun ULong.bic(n: Int): ULong = this.and(1UL.shl(n).inv())
|
||||
infix fun ULong.sex(n: Int): ULong {
|
||||
val sign = 1UL shl n+1
|
||||
return ((this and (sign.dec())) - (this and sign))
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user