A couple more CPU regs

This commit is contained in:
2023-09-16 18:19:41 +02:00
parent 9d2397d809
commit 4c4be0aa40
6 changed files with 343 additions and 8 deletions

View File

@@ -18,10 +18,15 @@ fun main(args: Array<String>) {
cpu.loadAbs(File(args[0]))
cpu.runState = CPU.RunState.RUNNING
cpu.pc = 0x80u
cpu.run()
val start = System.nanoTime()
val ninsn = cpu.run()
val end = System.nanoTime()
System.err.println("Halted at 0${cpu.pc.toString(8)}")
val time = (end-start).toDouble() / 1_000_000_000.0
println("Executed ${ninsn} in ${time}s: ${ninsn/time} i/s")
} finally {
println("Exiting")
console.stop()
}
}
}

View File

@@ -93,6 +93,21 @@ class CPU(val mbus: MemBus) {
set(value) {
psw = (psw and 0xFFFu) or (value and 0xFu)
}
private var pirq: UShort = 0u
set(value) {
val bitset = pirq shr 8
var maxp: UShort = 0u
for (i in 7 downTo 1) {
if (bitset bit i) {
maxp = i.toUShort() shl 1
break
}
}
field = value and 0xFE00u or maxp or (maxp shl 4)
}
private var cpu_err: UShort = 0u
set(value) { field = value and 0xFCu }
private var N: Boolean = false
private var C: Boolean = false
@@ -757,12 +772,15 @@ class CPU(val mbus: MemBus) {
}
fun step() {
try {
if (runState == RunState.HALTED) return
// TODO: handle PIRQ
for (i in (psw_priority + 1..<7).reversed()) {
for (i in 7 downTo (psw_priority + 1)) {
if (pirq bit 8+i) {
trap(0xA0u)
break
}
val source = mbus.unibus.checkInterrupt(i)
if (source != null) {
// we might have been waiting for an interrupt
@@ -784,10 +802,13 @@ class CPU(val mbus: MemBus) {
}
}
fun run() {
fun run(): Long {
var ninsn: Long = 0
while (runState == RunState.RUNNING) {
ninsn++
step()
}
return ninsn
}
fun trap(vector: UShort) {
@@ -799,14 +820,25 @@ class CPU(val mbus: MemBus) {
private inner class Registers: PAddressSpace {
override fun getw(addr: UInt): UShort = when (addr) {
0x3FFF0u -> (mbus.size shr 6).toUShort()
0x3FFF2u -> 0u // upper size
0x3FFF4u -> 0x1170u // system ID
0x3FFF6u -> cpu_err
0x3FFFAu -> pirq // PIRQ
0x3FFFCu -> 0x0u // stack limit
0x3FFFEu -> psw
else -> throw BusTimeoutError(addr)
}
override fun setw(addr: UInt, value: UShort) = when (addr) {
0x3_FFF0u , 0x3_FFF2u , 0x3_FFF4u, 0x3_FFF8u -> {} // read-only registers
0x3_FFF6u -> cpu_err = value
0x3_FFFAu -> pirq = value
0x3_FFFCu -> {} // stack limit
0x3_FFFEu -> psw = value
else -> {
println("Bus error at ${addr.toString(16)}")
println("Bus error at ${addr.toString(16)}: ${value.toString(16)}")
throw BusTimeoutError(addr)
}
}

View File

@@ -10,6 +10,7 @@ import com.thequux.mcpdp.ext.bit.bit
import com.thequux.mcpdp.ext.bit.maskSet
import java.io.InputStream
import java.io.OutputStream
import java.io.InterruptedIOException
import java.util.concurrent.Semaphore
import java.util.concurrent.locks.Lock
import java.util.concurrent.locks.LockSupport
@@ -110,6 +111,8 @@ class DL11(private var istr: InputStream, private val ostr: OutputStream, val re
break
}
}
} catch (_: InterruptedIOException) {
// Nothing to do; time to shut down
} catch (_: InterruptedException) {
// Nothing to do; time to shut down
}
@@ -124,4 +127,4 @@ class DL11(private var istr: InputStream, private val ostr: OutputStream, val re
super.stop()
reader?.interrupt()
}
}
}