Cleaned up order of writing condition codes and result of insns
This commit is contained in:
@@ -125,11 +125,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val dst = opc_dst(opcode)
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val v = op_loadw(dst)
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val res = (v shl 8) or (v shr 8)
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op_storw(dst, res)
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V = false
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C = false
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N = res bit 7
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Z = (res and 0xFFu) == 0.toUShort()
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op_storw(dst, res)
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} // SWAB
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else -> throw InvalidOpcodeException()
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} }
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@@ -154,35 +154,37 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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insnTable[0x0A] = {opcode ->
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when (opcode shr 6 and 3) {
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0 -> { // CLR
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op_storw(opc_dst(opcode), 0U)
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N = false
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V = false
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C = false
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Z = true
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op_storw(opc_dst(opcode), 0U)
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} // CLR
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1 -> { // COM
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val dst = opc_dst(opcode)
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val res = op_loadw(dst).inv().also { op_storw(dst, it) }
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val res = op_loadw(dst).inv()
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N = res bit 15
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Z = res == 0U.toUShort()
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C = true
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V = false
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op_storw(dst, res)
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} // COM
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2 -> { // INC
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = src.inc()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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V = res == 0x8000.toUShort()
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op_storw(dst, res)
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} // INC
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3 -> { // DEC
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val dst = opc_dst(opcode)
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val res = op_loadw(dst).dec().also { op_storw(dst, it) }
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val res = op_loadw(dst).dec()
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N = res bit 15
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Z = res == 0.toUShort()
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V = res == 0x7FFF.toUShort()
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op_storw(dst, res)
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} // DEC
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}
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} // CLR, COM, INC, DEC
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@@ -191,31 +193,31 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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0 -> { // NEG
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val dst = opc_dst(opcode)
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val res = op_loadw(dst).inv().inc()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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V = res == 0x8000.toUShort()
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C = !Z
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op_storw(dst, res)
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} // NEG
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1 -> { // ADC
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val dst = opc_dst(opcode)
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val c: UShort = if (C) 1u else 0u
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val res = (op_loadw(dst) + c).toUShort()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0u.toUShort()
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V = (res == 0x8000u.toUShort()) and C
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C = Z and C
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op_storw(dst, res)
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} // ADC
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2 -> {
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = if (C) src.dec() else src
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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V = res == 0x8000.toUShort()
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C = C and (src == 0.toUShort())
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op_storw(dst, res)
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} // SBC
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3 -> {
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val dst = op_loadw(opc_dst(opcode))
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@@ -232,41 +234,41 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = (src shr 1).bit(15, C)
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op_storw(dst, res)
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C = src bit 0
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N = res bit 15
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Z = res == 0.toUShort()
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V = N xor C
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op_storw(dst, res)
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} // ROR
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1 -> {
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = (src shl 1).bit(0, C)
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op_storw(dst, res)
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C = src bit 15
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N = res bit 15
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Z = res == 0.toUShort()
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V = N xor C
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op_storw(dst, res)
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} // ROL
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2 -> { // ASR
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val dst = opc_dst(opcode)
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val src = op_loadw(dst).toShort()
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val res = (src shr 1).toUShort()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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C = src bit 0
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V = N xor C
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op_storw(dst, res)
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} // ASR
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3 -> { // ASL
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val dst = opc_dst(opcode)
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val src = op_loadw(dst)
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val res = src shl 1
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op_storw(dst, res.toUShort())
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N = res bit 15
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Z = res == 0.toUShort()
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C = src and 0x8000u != 0u.toUShort()
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V = N xor C
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op_storw(dst, res)
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} // ASL
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}
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} // ROR, ROL, ASR, ASL
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@@ -289,14 +291,17 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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// memory ref
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core.getSpace(prv_mode).getw(src.toUShort(), dspace = false)
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}
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stack_push(v)
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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stack_push(v)
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} // MFPI // TODO
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2 -> {
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val v = stack_pop()
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val dest = opc_dst(opcode)
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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if (is_paddr_reg(dest)) {
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if (dest and 7u == 6u && prv_mode != cur_mode) {
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shadow_r6[prv_mode] = v
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@@ -306,14 +311,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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// memory ref
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core.getSpace(prv_mode).setw(dest.toUShort(), v, dspace = false)
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}
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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} // MTPI // TODO
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3 -> {
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op_storw(opc_dst(opcode), if (N) (-1).toUShort() else 0.toUShort())
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Z = !N
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V = false
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op_storw(opc_dst(opcode), if (N) (-1).toUShort() else 0.toUShort())
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} // SXT
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}
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} // MARK, MFPI, MTPI, SXT
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@@ -352,19 +354,19 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) and op_loadw(src).inv()
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0u.toUShort()
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V = false
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op_storw(dst, res)
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} // BIC
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for (i in 0x50..0x5F) insnTable[i] = { opcode -> // BIS
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val src = opc_src(opcode)
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) or op_loadw(src)
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op_storw(dst, res)
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N = res and 0x8000u != 0u.toUShort()
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Z = res == 0u.toUShort()
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V = false
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op_storw(dst, res)
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} // BIS
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for (i in 0x60..0x6F) insnTable[i] = { opcode -> // ADD
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val src = opc_src(opcode)
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@@ -373,12 +375,12 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val dstv = op_loadw(dst)
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val res = (srcv + dstv)
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val resw = res.toUShort()
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op_storw(dst, res.toUShort())
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N = resw > 0x7FFFu
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Z = resw == 0.toUShort()
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val src_sign = srcv and 0x8000u
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V = (src_sign == dstv and 0x8000u) && (src_sign != resw and 0x8000u)
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C = (res >= 0x10000u)
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op_storw(dst, res.toUShort())
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} // ADD
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insnTable[0x70] = { opcode -> // MUL
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val r = opcode shr 6 and 0x7
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@@ -493,10 +495,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val r = opcode shr 6 and 7
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val dst = opc_dst(opcode)
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val res = op_loadw(dst) xor registers[r]
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op_storw(dst, res)
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N = res bit 15
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Z = res == 0.toUShort()
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V = false
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op_storw(dst, res)
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} // XOR
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// 0x7A and 0x7C are undefined
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insnTable[0x7E] = { opcode -> // SOB
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@@ -526,33 +528,36 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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insnTable[0x8A] = { opcode ->
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when (opcode shr 6 and 3) {
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0 -> { // CLRB
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op_storb(opc_dstb(opcode), 0U)
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N = false
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V = false
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C = false
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Z = true
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op_storb(opc_dstb(opcode), 0U)
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} // CLRB
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1 -> { // COMB
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst).inv().also { op_storb(dst, it) }
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val res = op_loadb(dst).inv()
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N = res bit 7
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Z = res == 0U.toUByte()
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C = true
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V = false
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op_storb(dst, res)
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} // COMB
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2 -> { // INC
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2 -> { // INCB
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst).inc().also { op_storb(dst, it) }
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val res = op_loadb(dst).inc()
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N = res bit 7
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Z = res == 0.toUByte()
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V = res == 0x80.toUByte()
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op_storb(dst, res)
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} // INCB
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3 -> { // DEC
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst).dec().also { op_storb(dst, it) }
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val res = op_loadb(dst).dec()
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N = res bit 7
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Z = res == 0.toUByte()
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V = res == 0x7F.toUByte()
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op_storb(dst, res)
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} // DECB
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}
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} // CLRB, COMB, INCB, DECB
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@@ -561,31 +566,31 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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0 -> { // NEGB
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst).inv().inc()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0.toUByte()
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V = res == 0x8000.toUByte()
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C = !Z
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op_storb(dst, res)
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} // NEGB
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1 -> { // ADCB
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val dst = opc_dstb(opcode)
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val c: UShort = if (C) 1u else 0u
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val res = (op_loadb(dst) + c).toUByte()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0u.toUByte()
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V = (res == 0x80u.toUByte()) and C
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C = Z and C
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op_storb(dst, res)
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} // ADCB
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2 -> {
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val dst = opc_dstb(opcode)
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val src = op_loadb(dst)
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val res = if (C) src.dec() else src
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op_storb(dst, res)
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N = res bit 8
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Z = res == 0.toUByte()
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V = res == 0x80.toUByte()
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C = C and (src == 0.toUByte())
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op_storb(dst, res)
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} // SBCB
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3 -> {
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val dst = op_loadb(opc_dstb(opcode))
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@@ -602,41 +607,41 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val dst = opc_dstb(opcode)
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val src = op_loadb(dst)
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val res = (src shr 1).bit(7, C)
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op_storb(dst, res)
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C = src bit 0
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N = res bit 7
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Z = res == 0.toUByte()
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V = N xor C
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op_storb(dst, res)
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} // RORB
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1 -> {
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val dst = opc_dstb(opcode)
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val src = op_loadb(dst)
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val res = (src shl 1).bit(0, C)
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op_storb(dst, res)
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C = src bit 7
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N = res bit 7
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Z = res == 0.toUByte()
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V = N xor C
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op_storb(dst, res)
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} // ROLB
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2 -> { // ASRB
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val dst = opc_dstb(opcode)
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val src = op_loadb(dst).toByte()
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val res = (src shr 1).toUByte()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0.toUByte()
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C = src bit 0
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V = N xor C
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op_storb(dst, res)
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} // ASRB
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3 -> { // ASLB
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val dst = opc_dstb(opcode)
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val src = op_loadb(dst)
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val res = (src shl 1).toUByte()
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op_storw(dst, res.toUShort())
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N = res bit 7
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Z = res == 0.toUByte()
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C = src bit 7
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V = N xor C
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op_storw(dst, res.toUShort())
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} // ASLB
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}
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} // RORB, ROLB, ASRB, ASLB
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@@ -653,14 +658,17 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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// memory ref
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core.getSpace(prv_mode).getw(src.toUShort(), dspace = true)
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}
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stack_push(v)
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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stack_push(v)
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} // MFPD // TODO
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2 -> {
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val v = stack_pop()
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val dest = opc_dst(opcode)
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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if (is_paddr_reg(dest)) {
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if (dest and 7u == 6u && prv_mode != cur_mode) {
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shadow_r6[prv_mode] = v
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@@ -670,9 +678,6 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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// memory ref
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core.getSpace(prv_mode).setw(dest.toUShort(), v, dspace = true)
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}
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N = v bit 15
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Z = v == 0u.toUShort()
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V = false
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} // MTPD // TODO
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else -> { throw InvalidOpcodeException() } // Reserved
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}
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@@ -683,6 +688,9 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val dst = opc_dstb(opcode)
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val dstv = op_loadb(src)
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N = dstv bit 7
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Z = dstv == 0.toUByte()
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V = false
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if (is_paddr_reg(dst)) {
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op_storw(dst, dstv.toUShort() sex 8)
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dstv.toUShort() sex 8
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@@ -690,9 +698,6 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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op_storb(dst, dstv)
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dstv.toUShort()
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}
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N = dstv bit 7
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Z = dstv == 0.toUByte()
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V = false
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} // MOVB
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for (i in 0xA0..0xAF) insnTable[i] = { opcode -> // CMPB
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@@ -716,19 +721,19 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val src = opc_srcb(opcode)
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst) and op_loadb(src).inv()
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0u.toUByte()
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V = false
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op_storb(dst, res)
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} // BICB
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for (i in 0xD0..0xDF) insnTable[i] = { opcode -> // BISB
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val src = opc_srcb(opcode)
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val dst = opc_dstb(opcode)
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val res = op_loadb(dst) or op_loadb(src)
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op_storb(dst, res)
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N = res bit 7
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Z = res == 0u.toUByte()
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V = false
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op_storb(dst, res)
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} // BISB
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for (i in 0xE0..0xEF) insnTable[i] = { opcode ->
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val src = opc_src(opcode)
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@@ -736,11 +741,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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val srcv = op_loadw(src)
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val dstv = op_loadw(dst)
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val res = (dstv.toShort() - srcv.toShort())
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op_storw(dst, res.toUShort())
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N = res < 0
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Z = res == 0
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V = ((srcv bit 31) xor (dstv bit 15)) and ((srcv bit 15) == (res bit 31))
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C = (dst.toInt() + src.inv().inc().toInt()) < 0x1_0000
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op_storw(dst, res.toUShort())
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} // SUB
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// insnTable[0x0E] = // TODO: check this
|
||||
// insnTable[0x0F] = // TODO: check this
|
||||
|
||||
Reference in New Issue
Block a user