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Seems to get through tests, but never prints completion message

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TQ Hirsch
2023-09-19 23:43:29 +02:00
parent 11f2eb8d35
commit ac3496ed4f
1 changed files with 10 additions and 9 deletions
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19
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
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@@ -51,16 +51,15 @@ class CPU(val mbus: MemBus) {
res = res or (psw_priority shl 5) res = res or (psw_priority shl 5)
res = res or (cur_mode shl 14) or (prv_mode shl 12) res = res or (cur_mode shl 14) or (prv_mode shl 12)
res = res or (registerSet shl 11) res = res or (registerSet shl 11)
logger.debug("PSW: ${res.toString(16)}")
return res.toUShort() return res.toUShort()
} }
set(value) { set(value) {
var newpsw = value.toInt() var newpsw = value.toInt()
C = value bit 1 C = value bit 0
V = value bit 2 V = value bit 1
Z = value bit 3 Z = value bit 2
N = value bit 4 N = value bit 3
T = value bit 5 // TODO: handle suspended trap T = value bit 4 // TODO: handle suspended trap
psw_priority = newpsw shr 5 and 7 psw_priority = newpsw shr 5 and 7
registerSet = newpsw shr 11 and 1 registerSet = newpsw shr 11 and 1
cur_mode = newpsw shr 14 cur_mode = newpsw shr 14
@@ -134,6 +133,7 @@ class CPU(val mbus: MemBus) {
init { init {
val regs = Registers() val regs = Registers()
mbus.unibus.run { mbus.unibus.run {
attach(0x3FF78u, 1, regs)
attach(0x3FFE6u, 1, regs) attach(0x3FFE6u, 1, regs)
attach(0x3FFF8u, 3, regs) attach(0x3FFF8u, 3, regs)
attach(0x3FFF4u, 2, regs) attach(0x3FFF4u, 2, regs)
@@ -316,7 +316,6 @@ class CPU(val mbus: MemBus) {
} }
stack_push(registers[r]) stack_push(registers[r])
registers[r] = pc registers[r] = pc
System.err.println("JSR to ${dst.toString(16)}: ${opcode.toString(8)}")
pc = dst.toUShort() pc = dst.toUShort()
} // JSR } // JSR
0x0A00 -> when (opcode shr 6 and 3) { 0x0A00 -> when (opcode shr 6 and 3) {
@@ -875,7 +874,7 @@ class CPU(val mbus: MemBus) {
} }
fun trap(vector: UShort) { fun trap(vector: UShort) {
logger.debug("Trap to {}", vector.toString(8)) // logger.debug("Trap to {}", vector.toString(8))
val old_psw = psw val old_psw = psw
// update PSW first so that this gets pushed to the // update PSW first so that this gets pushed to the
psw = core.getw((vector + 2u).toUShort()) psw = core.getw((vector + 2u).toUShort())
@@ -886,6 +885,7 @@ class CPU(val mbus: MemBus) {
private inner class Registers: PAddressSpace { private inner class Registers: PAddressSpace {
override fun getw(addr: UInt): UShort = when (addr) { override fun getw(addr: UInt): UShort = when (addr) {
0x3FF78u -> 0u // Console switch/display
0x3FFE6u -> control_reg 0x3FFE6u -> control_reg
0x3FFF0u -> (mbus.size shr 6).toUShort() 0x3FFF0u -> (mbus.size shr 6).toUShort()
0x3FFF2u -> 0u // upper size 0x3FFF2u -> 0u // upper size
@@ -898,7 +898,8 @@ class CPU(val mbus: MemBus) {
} }
override fun setw(addr: UInt, value: UShort) = when (addr) { override fun setw(addr: UInt, value: UShort) = when (addr) {
0x3FFE6u -> control_reg = value 0x3_FF78u -> {} // console switch/display reg
0x3_FFE6u -> control_reg = value
0x3_FFF0u , 0x3_FFF2u , 0x3_FFF4u, 0x3_FFF8u -> {} // read-only registers 0x3_FFF0u , 0x3_FFF2u , 0x3_FFF4u, 0x3_FFF8u -> {} // read-only registers
0x3_FFF6u -> cpu_err = value 0x3_FFF6u -> cpu_err = value
0x3_FFFAu -> pirq = value 0x3_FFFAu -> pirq = value