From b512f1a42f31580b3a945b2a49a83ec308def246 Mon Sep 17 00:00:00 2001
From: TQ Hirsch <thequux@thequux.com>
Date: Sat, 30 Sep 2023 20:12:53 +0200
Subject: [PATCH] Fixed DATO/flag ordering for MOV. Still needs to be done for
 the rest of the insns

---
 src/main/kotlin/com/thequux/mcpdp/Loader.kt          |  6 +++---
 src/main/kotlin/com/thequux/mcpdp/core/CPU.kt        | 10 +++++++---
 src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt |  2 +-
 3 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/main/kotlin/com/thequux/mcpdp/Loader.kt b/src/main/kotlin/com/thequux/mcpdp/Loader.kt
index 9889246..538e8a2 100644
--- a/src/main/kotlin/com/thequux/mcpdp/Loader.kt
+++ b/src/main/kotlin/com/thequux/mcpdp/Loader.kt
@@ -65,13 +65,13 @@ fun CPU.loadAbs(infile: File) {
         if (cksum != 0) {
             throw Exception("Incorrect checksum: 0x${cksum.toString(16)}")
         }
-        logger.debug("Loading 0x${len.toString(16)} bytes at 0x${addr.toString(16)}")
+        logger.trace("Loading 0x${len.toString(16)} bytes at 0x${addr.toString(16)}")
         if (len == 0) {
             // end of file
-            logger.debug("Tape ended at ${pos+len+7}")
+            logger.trace("Tape ended at ${pos+len+7}")
             if (!(addr bit 0)){
                 this.pc = addr
-                logger.debug("Ready to run at ${addr.toString(8)}")
+                logger.trace("Ready to run at ${addr.toString(8)}")
             }
             return
         } else {
diff --git a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
index 5c1588c..7c86fcb 100644
--- a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
+++ b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
@@ -111,7 +111,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
                         registers[reg] = stack_pop()
                     } // RTS
                     in 0x98..0x9F -> {
-                        if (cur_mode == 0) psw_priority = opcode and 0x7
+                        if (cur_mode == 0) psw_priority_next = opcode and 0x7
                     } // SPL
                     in 0xA0..0xBF -> {
                         val flag = opcode bit 4
@@ -325,10 +325,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
                 val src = opc_src(opcode)
                 val dst = opc_dst(opcode)
                 op_loadw(src).also {
-                    op_storw(dst, it)
                     N = it bit 15
                     Z = it == 0.toUShort()
                     V = false
+                    op_storw(dst, it)
                 }
             } // MOV
             for (i in 0x20..0x2F) insnTable[i] = { opcode -> // CMP
@@ -796,7 +796,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
             registerSet = newpsw shr 11 and 1
             cur_mode = newpsw shr 14
             prv_mode = newpsw shr 12 and 3
-            psw_priority = newpsw shr 5 and 7
+            psw_priority_next = newpsw shr 5 and 7
         } else {
             registerSet = registerSet or (newpsw shr 11 and 1)
             cur_mode = cur_mode or (newpsw shr 14 and 3)
@@ -814,6 +814,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
         }
     private var prv_mode: Int = 0
     private var psw_priority: Int = 0
+    private var psw_priority_next: Int = 0
     var pc: UShort
         get() = registers[7]
         set(value) {
@@ -1122,8 +1123,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
         }
 
         if (runState == RunState.WAIT_FOR_INTERRUPT) {
+            // Note that it is impossible to have a pending priority change at the same time as a WAIT insn
             return
         }
+        psw_priority = psw_priority_next
 
         // Proceed to handling instruction
         try {
@@ -1188,6 +1191,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
         val old_psw = psw
         val newPSW = core.getSpace(0).getw((vector + 2u).toUShort()) and 0xCFFFu or (cur_mode shl 12).toUShort()
         setPSW(newPSW, true)
+        psw_priority = psw_priority_next // calling a vector sets priority immediately
         stack_push(old_psw)
         stack_push(pc)
         pc = core.getw(vector)
diff --git a/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt b/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt
index b5411cc..05eb979 100644
--- a/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt
+++ b/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt
@@ -42,7 +42,7 @@ class DL11(private var istr: InputStream, private val ostr: OutputStream, val re
     override fun reset() {
         rcsr = 0x0u
         rcsr = 0x0u
-//        xcsr = 0x80u
+        xcsr = 0x80u
 
         intrRcv.level = false
         intrXmit.level = false