diff --git a/src/main/kotlin/com/thequux/mcpdp/cli/Cli.kt b/src/main/kotlin/com/thequux/mcpdp/cli/Cli.kt index 7654cc0..76812c3 100644 --- a/src/main/kotlin/com/thequux/mcpdp/cli/Cli.kt +++ b/src/main/kotlin/com/thequux/mcpdp/cli/Cli.kt @@ -28,6 +28,9 @@ class Cli: Callable { @Option(names = ["-t", "--trace"]) private var traceLength: Int = 0 + @Option(names = ["--live"]) + private var liveTrace = false + @Option(names = ["-g", "--go"], description = ["Start address in octal. Ignored if odd"], converter = [ OctalParamConverter::class ]) private var startAddress: Int = 1 diff --git a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt index f85c6cb..3124ff1 100644 --- a/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt +++ b/src/main/kotlin/com/thequux/mcpdp/core/CPU.kt @@ -1088,7 +1088,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) { // we might have been waiting for an interrupt runState = RunState.RUNNING val vector = source.vector -// logger.debug("Unibus interrupt at pri {} to {}", i, vector) + mbus.unibus.logger.debug("DATIP: {} @ {}", vector.toOctal(), i) callVector(vector) source.handled() break @@ -1097,7 +1097,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) { } else { val pirqLvl = pirq.toInt() shr 1 and 7; if (pirqLvl > psw_priority) { - logger.debug("PIRQ{} trap to 0xA0", pirqLvl) +// logger.debug("PIRQ{} trap to 0xA0", pirqLvl) callVector(0xA0u) } } @@ -1158,10 +1158,14 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) { atBreakpoint = false var ninsn: Long = 0 while (runState == RunState.RUNNING && ninsn < nstep && !atBreakpoint) { - ninsn++ - step() if (pc == breakpoint) { atBreakpoint = true + ninsn = ninsn // Dummy statement to set debugger bkpt on +// continue + } + if (!atBreakpoint) { + ninsn++ + step() } } return ninsn diff --git a/src/main/kotlin/com/thequux/mcpdp/core/PagingUnit.kt b/src/main/kotlin/com/thequux/mcpdp/core/PagingUnit.kt index e91f78f..1e04611 100644 --- a/src/main/kotlin/com/thequux/mcpdp/core/PagingUnit.kt +++ b/src/main/kotlin/com/thequux/mcpdp/core/PagingUnit.kt @@ -314,8 +314,8 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace { val regs = ConfigRegisters() unibus.run { deviceView = UnibusMap() - attach(0x3_F480u, 6, PdPair(itabs[0], dtabs[0])) - attach(0x3_F4C0u, 6, PdPair(itabs[1], dtabs[1])) + attach(0x3_F480u, 6, PdPair(itabs[1], dtabs[1])) + attach(0x3_F4C0u, 6, PdPair(itabs[0], dtabs[0])) attach(0x3_FF80u, 6, PdPair(itabs[2], dtabs[2])) // User PAR/PDR attach(0x3_FF7Au, 1, regs) // MMR0 attach(0x3_FF7Cu, 2, regs) // MMR1-2 diff --git a/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt b/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt index c81abf7..b5411cc 100644 --- a/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt +++ b/src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt @@ -76,7 +76,10 @@ class DL11(private var istr: InputStream, private val ostr: OutputStream, val re if (value bit 0) {rcsr = rcsr bic 7 } } 2 -> { rcsr = rcsr bic 7 } - 4 -> xcsr = xcsr.maskSet(value, 0x0045u) + 4 -> { + xcsr = xcsr.maskSet(value, 0x0045u) + if (!(xcsr bit 6)) intrXmit.level = false + } 6 -> { val b = value.toInt() and 0xFF if (xcsr bit 2) { diff --git a/src/main/kotlin/com/thequux/mcpdp/peripheral/Unibus.kt b/src/main/kotlin/com/thequux/mcpdp/peripheral/Unibus.kt index 5d2b6bc..c7ddd4a 100644 --- a/src/main/kotlin/com/thequux/mcpdp/peripheral/Unibus.kt +++ b/src/main/kotlin/com/thequux/mcpdp/peripheral/Unibus.kt @@ -74,7 +74,7 @@ class Unibus: PAddressSpace, Subregion(12, 6) { /// The view of the unibus from a device var deviceView: PAddressSpace = this internal set - private val logger = LoggerFactory.getLogger(this.javaClass) + internal val logger = LoggerFactory.getLogger(this.javaClass) private val queue: Array> = Array(8) { Vector(4) } private val devices: HashSet = HashSet()