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Fixed SPL being executable without privilege

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This commit is contained in:
TQ Hirsch
2023-09-30 11:31:46 +02:00
parent 709eddc225
commit 3bbeaa9b8e
2 changed files with 8 additions and 8 deletions
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4
src/main/kotlin/Main.kt
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@@ -26,7 +26,7 @@ fun main(args: Array<String>) {
val tracer = Tracer()
val loggingCollector = LoggingCollector()
// tracer.addCollector(loggingCollector)
val recorder = FlightRecorder(24)
val recorder = FlightRecorder(3000)
tracer.addCollector(recorder)
var cpu = CPU(mbus, if (CPU.debugMode) tracer else NullTracer())
val console = DL11(mbus.unibus, tb.input(), tb.output()).apply { mount(mbus.unibus) }
@@ -52,7 +52,7 @@ fun main(args: Array<String>) {
System.err.println("Halted at 0${cpu.pc.toString(8)}")
val time = (end - start).toDouble() / 1_000_000_000.0
println("Executed ${ninsn} in ${time}s: ${ninsn / time / 1_000_000} MIPS")
System.err.println("Executed ${ninsn} in ${time}s: ${ninsn / time / 1_000_000} MIPS")
} finally {
println("Exiting")
console.stop()

12
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
View File

@@ -111,7 +111,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
registers[reg] = stack_pop()
} // RTS
in 0x98..0x9F -> {
psw_priority = opcode and 0x7
if (cur_mode == 0) psw_priority = opcode and 0x7
} // SPL
in 0xA0..0xBF -> {
val flag = opcode bit 4
@@ -1155,7 +1155,8 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
var ninsn: Long = 0
while (runState == RunState.RUNNING && ninsn < nstep) {
ninsn++
if (pc == 0x2E54.toUShort()) {
if (pc == 0x3224.toUShort()) {
runState = runState
runState = RunState.HALTED
}
step()
@@ -1165,8 +1166,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
fun callVector(vector: UShort) {
val old_psw = psw
// update PSW first so that this gets pushed to the
val newPSW = core.getw((vector + 2u).toUShort()) or (cur_mode shl 12).toUShort()
val newPSW = core.getw((vector + 2u).toUShort()) and 0xCFFFu or (cur_mode shl 12).toUShort()
setPSW(newPSW, true)
stack_push(old_psw)
stack_push(pc)
@@ -1201,9 +1201,9 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
0x3_FFFAu -> pirq = value
0x3_FFFCu -> stack_limit = value and 0xFF00u // stack limit
0x3_FFFEu -> {
setPSW(value or (cur_mode.toUShort() shl 12), true)
setPSW(value, true)
// explicitly switch RS if necessary
registerSet = (value shr 11 and 1u).toInt()
// registerSet = (value shr 11 and 1u).toInt()
} // writing to PSW can only increase current mode
else -> {
println("Bus error at ${addr.toString(16)}: ${value.toString(16)}")