Got to end of test, but fails to successfully end test :-/

This commit is contained in:
2023-09-30 16:14:59 +02:00
parent c8c8297765
commit 6052c9a0c0

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@@ -1134,9 +1134,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
}
is NonExistentMemoryError -> {
cpu_err = cpu_err or CPU_ERR_NXM
logger.warn("NXM at {}", error.addr.toOctal())
setTrap(TrapReason.NXM)
}
is BusTimeoutError -> {
logger.warn("TMO at {}", error.addr.toOctal())
cpu_err = cpu_err or CPU_ERR_UNIBUS_TIMEOUT
setTrap(TrapReason.NXM)
}
@@ -1177,7 +1179,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
fun callVector(vector: UShort) {
val old_psw = psw
val newPSW = core.getw((vector + 2u).toUShort()) and 0xCFFFu or (cur_mode shl 12).toUShort()
val newPSW = core.getSpace(0).getw((vector + 2u).toUShort()) and 0xCFFFu or (cur_mode shl 12).toUShort()
setPSW(newPSW, true)
stack_push(old_psw)
stack_push(pc)
@@ -1225,10 +1227,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
fun checkSP(addr: UShort): UShort {
if (cur_mode != 0) return addr
if (sp < stack_limit + 224u || sp.toInt() and 0xFFFE == 0xFFFE) {
if (addr < stack_limit + 224u || addr.toInt() and 0xFFFE == 0xFFFE) {
trapRed()
throw EndCycle()
} else if (sp < stack_limit + 256u) {
} else if (addr < stack_limit + 256u) {
// logger.warn("Stack YLW")
// stack limit yellow
cpu_err = cpu_err or CPU_ERR_STK_YLW