Got 60 insns further in EKBA

src/main/kotlin/com/thequux/mcpdp/core/CPU.kt

@@ -6,6 +6,7 @@ import com.thequux.mcpdp.util.Disassembler
 import com.thequux.mcpdp.util.ProgrammerError
 import org.slf4j.Logger
 import org.slf4j.LoggerFactory
+import java.lang.StringBuilder
 import kotlin.math.log
 
 /// The main CPU
@@ -202,19 +203,19 @@ class CPU(val mbus: MemBus) {
     }
 
     private fun op_storw(spec: UInt, value: UShort, dspace: Boolean = true) {
-        val addr = (spec and 0xFFFFu).toUShort()
+        val addr = (spec and 0xFFFFu)
         if (is_paddr_reg(spec)) {
             // register
             registers[addr.toInt()] = value
         } else {
-            core.setw(addr, value, dspace)
+            core.setw(addr.toUShort(), value, dspace)
         }
     }
 
     private fun op_loadw(spec: UInt, dspace: Boolean=true): UShort {
         val addr = (spec and 0xFFFFu).toUShort()
         return if (is_paddr_reg(spec)) {
-            (registers[addr.toInt()] and 0xFFu)
+            registers[addr.toInt()]
         } else {
             core.getw(addr, dspace)
         }
@@ -286,6 +287,7 @@ class CPU(val mbus: MemBus) {
                         if (opcode bit 1) V = flag
                         if (opcode bit 2) Z = flag
                         if (opcode bit 3) N = flag
+//                        debugFlags()
                     } // Scc/Ccc
                     in 0xC0..0xFF -> {
                         val dst = opc_dst(opcode)
@@ -335,10 +337,15 @@ class CPU(val mbus: MemBus) {
                     } // COM
                     2 -> { // INC
                         val dst = opc_dst(opcode)
-                        val res = op_loadw(dst).inc().also { op_storw(dst, it) }
+                        val src = op_loadw(dst)
+                        val res = src.inc()
+                        op_storw(dst, res)
                         N = res bit 15
                         Z = res == 0.toUShort()
                         V = res == 0x8000.toUShort()
+                        debugFlags()
+                        logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${src.toString(16)}")
+
                     } // INC
                     3 -> { // DEC
                         val dst = opc_dst(opcode)
@@ -396,6 +403,8 @@ class CPU(val mbus: MemBus) {
                         N = res bit 15
                         Z = res == 0.toUShort()
                         V = N xor C
+//                        debugFlags()
+//                        logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}/${op_loadw(dst).toString(16)}, SRC: ${src.toString(16)}, C: ${src bit 15}")
                     } // ROR
                     1 -> {
                         val dst = opc_dst(opcode)
@@ -406,6 +415,8 @@ class CPU(val mbus: MemBus) {
                         N = res bit 15
                         Z = res == 0.toUShort()
                         V = N xor C
+//                        debugFlags()
+//                        logger.debug("RES: ${res.toString(16)}, SRC: ${src.toString(16)}, C: ${src bit 15}")
                     } // ROL
                     2 -> { // ASR
                         val dst = opc_dst(opcode)
@@ -438,7 +449,7 @@ class CPU(val mbus: MemBus) {
                     1 -> { throw InvalidOpcodeException() } // MFPI // TODO
                     2 -> { throw InvalidOpcodeException() } // MTPI // TODO
                     3 -> {
-                        op_storw(opc_dst(opcode), if (N) 0.toUShort() else (-1).toUShort())
+                        op_storw(opc_dst(opcode), if (N) (-1).toUShort() else 0.toUShort())
                         Z = !N
                         V = false
                     } // SXT
@@ -794,6 +805,17 @@ class CPU(val mbus: MemBus) {
         }
     }
 
+    private fun debugFlags() {
+        if (logger.isDebugEnabled) {
+            val res = StringBuilder()
+            if (N) res.append('N')
+            if (Z) res.append('Z')
+            if (C) res.append('C')
+            if (V) res.append('V')
+            logger.debug("Flags: $res")
+        }
+    }
+
     fun step() {
         try {
             if (runState == RunState.HALTED) return

src/main/kotlin/com/thequux/mcpdp/util/DebugTools.kt

@@ -21,6 +21,20 @@ class Disassembler(val core: VAddressSpace) {
 
     private fun fmt(opcode: String, vararg args: String): String {
         val res = StringBuilder()
+
+        var tpc = opc
+        var bytes = 0
+        while (tpc != vpc) {
+            bytes += 2
+            res.append(core.getw(tpc, dspace = false).toString(16).padStart(4, '0'))
+            res.append('.')
+            tpc = tpc.inc().inc()
+        }
+        while (bytes < 6) {
+            res.append("----.")
+            bytes += 2
+        }
+        res.append('\t')
         res.append(opcode.uppercase())
 
         for ((index, arg) in args.withIndex()) {
@@ -72,7 +86,7 @@ class Disassembler(val core: VAddressSpace) {
 
     private fun br_rel(opc: String): String {
         val rel = (opcode and 0xFF) - (opcode and 0x80 shl 1)
-        val dst = (vpc.toInt() + rel).toUShort()
+        val dst = (vpc.toInt() + rel.shl(1)).toUShort()
         return fmt(opc, dst.toString(8))
     }
 
@@ -83,7 +97,8 @@ class Disassembler(val core: VAddressSpace) {
     }
 
     fun dasm_at(loc: UShort): String {
-        var vpc = loc
+        vpc = loc
+        opc = loc
 
         opcode = core.getw(vpc, dspace = false).toInt()
         vpc = (vpc + 2u).toUShort()
@@ -108,7 +123,7 @@ class Disassembler(val core: VAddressSpace) {
                             if (opcode bit 1) items.add("SEZ")
                             if (opcode bit 2) items.add("SEV")
                             if (opcode bit 3) items.add("SEN")
-                            items.joinToString(" ")
+                            fmt(items.joinToString(" "))
                         } // Scc/Ccc
                         in 0xC0..0xFF -> fmt("SWAB", dst()) // SWAB
                         else -> throw InvalidOpcodeException()