Fixed memory map calculation; now gets completely through the test suite

This commit is contained in:
2023-09-29 01:15:47 +02:00
parent d5a36eac84
commit c2f38a4b50
4 changed files with 18 additions and 12 deletions

View File

@@ -38,9 +38,10 @@ fun main(args: Array<String>) {
cpu.pc = 0x80u
val start = System.nanoTime()
// var ninsn = cpu.run(600000000)
var ninsn = cpu.run(376670)
// var ninsn = cpu.run(419380)
var ninsn = cpu.run(13300)
cpu.tracer = tracer
ninsn += cpu.run(30)
ninsn += cpu.run(100)
cpu.dumpReg()
val end = System.nanoTime()

View File

@@ -1050,7 +1050,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
if (trapReq != 0) {
for (cause in TrapReason.entries.reversed()) {
if (trapReq and cause.mask != 0) {
// logger.warn("Trapping because $cause")
logger.warn("Trapping because $cause")
try {
callVector(cause.vector)
} finally {
@@ -1066,7 +1066,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
else if (mbus.unibus.interruptPending) {
for (i in 7 downTo (psw_priority + 1)) {
if (pirq bit 8 + i) {
// logger.debug("PIRQ{} trap to 0xA0", i)
logger.debug("PIRQ{} trap to 0xA0", i)
callVector(0xA0u)
break
}
@@ -1075,7 +1075,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
// we might have been waiting for an interrupt
runState = RunState.RUNNING
val vector = source.vector
// logger.debug("Unibus interrupt at pri {} to {}", i, vector)
logger.debug("Unibus interrupt at pri {} to {}", i, vector)
callVector(vector)
source.handled()
break
@@ -1084,7 +1084,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
} else {
val pirqLvl = pirq.toInt() shr 1 and 7;
if (pirqLvl > psw_priority) {
// logger.debug("PIRQ{} trap to 0xA0", pirqLvl)
logger.debug("PIRQ{} trap to 0xA0", pirqLvl)
callVector(0xA0u)
}
}

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@@ -5,6 +5,7 @@ import com.thequux.mcpdp.ext.bit.*
import com.thequux.mcpdp.peripheral.Unibus
import com.thequux.mcpdp.util.ProgrammerError
import kotlin.math.max
import kotlin.math.min
enum class AccessAction {
Allow,
@@ -77,8 +78,8 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
val unibusMap: PAddressSpace = UnibusMap()
private inner class PageTable(val mode: Int, val dspace: Boolean) {
val par = UShortArray(16) { 0U }
val pdr = Array(16) { PDR() }
val par = UShortArray(8) { 0U }
val pdr = Array(8) { PDR() }
fun setMmr0(causeBit: Int, apf: Int, completed: Boolean = false) {
@@ -121,7 +122,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
throw EndCycle()
}
}
val tmp1 = addr.toUInt() + (par.toUInt() shl 6) and mapMode.addrMask
val tmp1 = addr.toUInt().and(0x1FFFu) + (par.toUInt() shl 6) and mapMode.addrMask
if (tmp1 and mapMode.hipageMask == mapMode.hipageMask) {
return tmp1 or 0x3C_0000u
} else {
@@ -142,7 +143,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
enable22bit -> MManMode.MM_22
else -> MManMode.MM_18
}
modeSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace
modeSpace = if (mapMode.mmanEnable) modeVTabs[min(mode, 2)] else noMmanSpace
}
fun getSpace(mode: Int): VAddressSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace
@@ -172,7 +173,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
private inner class ModeVSpace(private val iSpace: PageTable, private val dSpace: PageTable, var useDSpace: Boolean): VAddressSpace {
private fun getSpace(dspace: Boolean): PageTable = if (dspace) dSpace else iSpace
private fun getSpace(dspace: Boolean): PageTable = if (dspace && useDSpace) dSpace else iSpace
override fun getw(addr: UShort, dspace: Boolean): UShort = pspace.getw(getSpace(dspace).map(addr, write = false))
override fun getb(addr: UShort): UByte = pspace.getb(dSpace.map(addr, write = false))

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@@ -86,7 +86,11 @@ class Disassembler {
fun dasm_at(loc: UShort, istream: UShortArray): String {
opc = loc
this.istream = istream
opcode = istream[0].toInt()
try {
opcode = istream[0].toInt()
} catch(_: IndexOutOfBoundsException) {
return fmt("????")
}
vpc = 1
try {