Fixed memory map calculation; now gets completely through the test suite
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@@ -38,9 +38,10 @@ fun main(args: Array<String>) {
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cpu.pc = 0x80u
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cpu.pc = 0x80u
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val start = System.nanoTime()
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val start = System.nanoTime()
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// var ninsn = cpu.run(600000000)
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// var ninsn = cpu.run(600000000)
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var ninsn = cpu.run(376670)
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// var ninsn = cpu.run(419380)
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var ninsn = cpu.run(13300)
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cpu.tracer = tracer
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cpu.tracer = tracer
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ninsn += cpu.run(30)
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ninsn += cpu.run(100)
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cpu.dumpReg()
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cpu.dumpReg()
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val end = System.nanoTime()
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val end = System.nanoTime()
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@@ -1050,7 +1050,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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if (trapReq != 0) {
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if (trapReq != 0) {
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for (cause in TrapReason.entries.reversed()) {
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for (cause in TrapReason.entries.reversed()) {
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if (trapReq and cause.mask != 0) {
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if (trapReq and cause.mask != 0) {
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// logger.warn("Trapping because $cause")
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logger.warn("Trapping because $cause")
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try {
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try {
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callVector(cause.vector)
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callVector(cause.vector)
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} finally {
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} finally {
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@@ -1066,7 +1066,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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else if (mbus.unibus.interruptPending) {
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else if (mbus.unibus.interruptPending) {
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for (i in 7 downTo (psw_priority + 1)) {
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for (i in 7 downTo (psw_priority + 1)) {
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if (pirq bit 8 + i) {
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if (pirq bit 8 + i) {
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// logger.debug("PIRQ{} trap to 0xA0", i)
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logger.debug("PIRQ{} trap to 0xA0", i)
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callVector(0xA0u)
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callVector(0xA0u)
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break
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break
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}
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}
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@@ -1075,7 +1075,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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// we might have been waiting for an interrupt
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// we might have been waiting for an interrupt
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runState = RunState.RUNNING
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runState = RunState.RUNNING
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val vector = source.vector
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val vector = source.vector
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// logger.debug("Unibus interrupt at pri {} to {}", i, vector)
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logger.debug("Unibus interrupt at pri {} to {}", i, vector)
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callVector(vector)
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callVector(vector)
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source.handled()
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source.handled()
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break
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break
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@@ -1084,7 +1084,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
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} else {
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} else {
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val pirqLvl = pirq.toInt() shr 1 and 7;
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val pirqLvl = pirq.toInt() shr 1 and 7;
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if (pirqLvl > psw_priority) {
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if (pirqLvl > psw_priority) {
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// logger.debug("PIRQ{} trap to 0xA0", pirqLvl)
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logger.debug("PIRQ{} trap to 0xA0", pirqLvl)
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callVector(0xA0u)
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callVector(0xA0u)
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}
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}
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}
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}
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@@ -5,6 +5,7 @@ import com.thequux.mcpdp.ext.bit.*
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import com.thequux.mcpdp.peripheral.Unibus
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import com.thequux.mcpdp.peripheral.Unibus
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import com.thequux.mcpdp.util.ProgrammerError
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import com.thequux.mcpdp.util.ProgrammerError
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import kotlin.math.max
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import kotlin.math.max
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import kotlin.math.min
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enum class AccessAction {
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enum class AccessAction {
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Allow,
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Allow,
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@@ -77,8 +78,8 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
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val unibusMap: PAddressSpace = UnibusMap()
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val unibusMap: PAddressSpace = UnibusMap()
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private inner class PageTable(val mode: Int, val dspace: Boolean) {
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private inner class PageTable(val mode: Int, val dspace: Boolean) {
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val par = UShortArray(16) { 0U }
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val par = UShortArray(8) { 0U }
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val pdr = Array(16) { PDR() }
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val pdr = Array(8) { PDR() }
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fun setMmr0(causeBit: Int, apf: Int, completed: Boolean = false) {
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fun setMmr0(causeBit: Int, apf: Int, completed: Boolean = false) {
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@@ -121,7 +122,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
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throw EndCycle()
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throw EndCycle()
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}
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}
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}
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}
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val tmp1 = addr.toUInt() + (par.toUInt() shl 6) and mapMode.addrMask
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val tmp1 = addr.toUInt().and(0x1FFFu) + (par.toUInt() shl 6) and mapMode.addrMask
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if (tmp1 and mapMode.hipageMask == mapMode.hipageMask) {
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if (tmp1 and mapMode.hipageMask == mapMode.hipageMask) {
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return tmp1 or 0x3C_0000u
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return tmp1 or 0x3C_0000u
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} else {
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} else {
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@@ -142,7 +143,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
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enable22bit -> MManMode.MM_22
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enable22bit -> MManMode.MM_22
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else -> MManMode.MM_18
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else -> MManMode.MM_18
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}
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}
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modeSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace
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modeSpace = if (mapMode.mmanEnable) modeVTabs[min(mode, 2)] else noMmanSpace
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}
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}
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fun getSpace(mode: Int): VAddressSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace
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fun getSpace(mode: Int): VAddressSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace
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@@ -172,7 +173,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
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private inner class ModeVSpace(private val iSpace: PageTable, private val dSpace: PageTable, var useDSpace: Boolean): VAddressSpace {
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private inner class ModeVSpace(private val iSpace: PageTable, private val dSpace: PageTable, var useDSpace: Boolean): VAddressSpace {
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private fun getSpace(dspace: Boolean): PageTable = if (dspace) dSpace else iSpace
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private fun getSpace(dspace: Boolean): PageTable = if (dspace && useDSpace) dSpace else iSpace
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override fun getw(addr: UShort, dspace: Boolean): UShort = pspace.getw(getSpace(dspace).map(addr, write = false))
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override fun getw(addr: UShort, dspace: Boolean): UShort = pspace.getw(getSpace(dspace).map(addr, write = false))
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override fun getb(addr: UShort): UByte = pspace.getb(dSpace.map(addr, write = false))
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override fun getb(addr: UShort): UByte = pspace.getb(dSpace.map(addr, write = false))
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@@ -86,7 +86,11 @@ class Disassembler {
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fun dasm_at(loc: UShort, istream: UShortArray): String {
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fun dasm_at(loc: UShort, istream: UShortArray): String {
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opc = loc
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opc = loc
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this.istream = istream
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this.istream = istream
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opcode = istream[0].toInt()
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try {
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opcode = istream[0].toInt()
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} catch(_: IndexOutOfBoundsException) {
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return fmt("????")
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}
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vpc = 1
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vpc = 1
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try {
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try {
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