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Makes it all the way through EKBB

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TQ Hirsch
2023-09-30 17:08:43 +02:00
parent 6052c9a0c0
commit d90304b5fd
3 changed files with 22 additions and 11 deletions
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4
src/main/kotlin/com/thequux/mcpdp/cli/Cli.kt
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@@ -40,6 +40,9 @@ class Cli: Callable<Int> {
@Option(names = ["-c", "--count"], description = ["Max number of instructions to run. 0 is infinite"]) @Option(names = ["-c", "--count"], description = ["Max number of instructions to run. 0 is infinite"])
private var maxInsns: Long = 0 private var maxInsns: Long = 0
@Option(names = ["-s", "--switch"], description = ["Value of the switch register, in octal"], defaultValue = "0", converter = [OctalParamConverter::class])
private var switchReg: Int = 0
override fun call(): Int { override fun call(): Int {
val tb = org.jline.terminal.TerminalBuilder.terminal() val tb = org.jline.terminal.TerminalBuilder.terminal()
var mbus = MemBus(65536) var mbus = MemBus(65536)
@@ -52,6 +55,7 @@ class Cli: Callable<Int> {
} }
var cpu = CPU(mbus, if (traceLength > 0 || CPU.debugMode) tracer else NullTracer()) var cpu = CPU(mbus, if (traceLength > 0 || CPU.debugMode) tracer else NullTracer())
val console = DL11(mbus.unibus, tb.input(), tb.output()).apply { mount(mbus.unibus) } val console = DL11(mbus.unibus, tb.input(), tb.output()).apply { mount(mbus.unibus) }
cpu.switchReg = switchReg.toUShort()
try { try {

27
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
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@@ -747,6 +747,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
} }
} }
var switchReg: UShort = 0u
private var atBreakpoint: Boolean = false private var atBreakpoint: Boolean = false
private var allowT: Boolean = true private var allowT: Boolean = true
private var control_reg: UShort = 0u private var control_reg: UShort = 0u
@@ -1048,15 +1049,21 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
fun trapRed() { fun trapRed() {
// This is handled separately because otherwise the stack push // This is handled separately because otherwise the stack push
// would itself trigger a red trap // would itself trigger a red trap
// logger.warn("Stack RED") logger.trace("Stack RED")
cpu_err = cpu_err or CPU_ERR_STK_RED cpu_err = cpu_err or CPU_ERR_STK_RED
val old_psw = psw val old_psw = psw
setPSW(core.getw(6u), true) setPSW(core.getSpace(0).getw(6u), true)
core.setw(2u, old_psw) if (cur_mode == 0) {
core.setw(0u, pc) sp = 4u
sp = 0u } else {
shadow_r6[0] = 4u
}
// manually implement stack_push to inhibit red trap
core.setw((sp-2u).toUShort(), old_psw)
core.setw((sp-4u).toUShort(), pc)
sp = (sp - 4u).toUShort()
trapReq = trapReq and TrapReason.RED.clear.inv() trapReq = trapReq and TrapReason.RED.clear.inv()
pc = core.getw(4u) pc = core.getSpace(0).getw(4u)
} }
fun step() { fun step() {
@@ -1134,11 +1141,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
} }
is NonExistentMemoryError -> { is NonExistentMemoryError -> {
cpu_err = cpu_err or CPU_ERR_NXM cpu_err = cpu_err or CPU_ERR_NXM
logger.warn("NXM at {}", error.addr.toOctal()) logger.trace("NXM at {}", error.addr.toOctal())
setTrap(TrapReason.NXM) setTrap(TrapReason.NXM)
} }
is BusTimeoutError -> { is BusTimeoutError -> {
logger.warn("TMO at {}", error.addr.toOctal()) logger.trace("TMO at {}", error.addr.toOctal())
cpu_err = cpu_err or CPU_ERR_UNIBUS_TIMEOUT cpu_err = cpu_err or CPU_ERR_UNIBUS_TIMEOUT
setTrap(TrapReason.NXM) setTrap(TrapReason.NXM)
} }
@@ -1192,7 +1199,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
private inner class Registers: PAddressSpace { private inner class Registers: PAddressSpace {
override fun getw(addr: UInt): UShort = when (addr) { override fun getw(addr: UInt): UShort = when (addr) {
0x3FF78u -> 0x70u // Console switch/display 0x3FF78u -> switchReg // Console switch/display
0x3FFE6u -> control_reg 0x3FFE6u -> control_reg
0x3FFF0u -> (mbus.size shr 6).toUShort() 0x3FFF0u -> (mbus.size shr 6).toUShort()
0x3FFF2u -> 0u // upper size 0x3FFF2u -> 0u // upper size
@@ -1206,7 +1213,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
override fun setw(addr: UInt, value: UShort) = when (addr) { override fun setw(addr: UInt, value: UShort) = when (addr) {
0x3_FF78u -> { 0x3_FF78u -> {
System.err.print("\u001b]0;${value.toOctal()}\u0007") // System.err.print("\u001b]0;${value.toOctal()}\u0007")
} // console switch/display reg } // console switch/display reg
0x3_FFE6u -> control_reg = value 0x3_FFE6u -> control_reg = value
0x3_FFF0u , 0x3_FFF2u , 0x3_FFF4u, 0x3_FFF8u -> {} // read-only registers 0x3_FFF0u , 0x3_FFF2u , 0x3_FFF4u, 0x3_FFF8u -> {} // read-only registers

2
src/main/kotlin/com/thequux/mcpdp/core/PagingUnit.kt
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@@ -163,7 +163,7 @@ class PagingUnit(val pspace: PAddressSpace, val cpu: CPU): VAddressSpace {
modeSpace = if (mapMode.mmanEnable) modeVTabs[min(mode, 2)] else noMmanSpace modeSpace = if (mapMode.mmanEnable) modeVTabs[min(mode, 2)] else noMmanSpace
} }
fun getSpace(mode: Int): VAddressSpace = if (mapMode.mmanEnable) modeVTabs[max(mode, 2)] else noMmanSpace fun getSpace(mode: Int): VAddressSpace = if (mapMode.mmanEnable) modeVTabs[min(mode, 2)] else noMmanSpace
fun logIncrement(register: Int, amount: Int) { fun logIncrement(register: Int, amount: Int) {
assert(register in 0..7) assert(register in 0..7)