4 Commits

Author	SHA1	Message	Date
TQ Hirsch	1bc7f93d57	Added rest of the CPU registers and logging	2023-09-18 14:40:23 +02:00
TQ Hirsch	0d3dfb5a37	Many changes	2023-09-10 20:53:10 +02:00
TQ Hirsch	a1daa4c4b3	Fully implemented CPU and memory busses, but not yet tested	2023-08-31 13:46:28 +02:00
TQ Hirsch	35736a5fd2	Initial commit	2023-08-28 14:00:07 +02:00