2 Commits

Author	SHA1	Message	Date
TQ Hirsch	1bc7f93d57	Added rest of the CPU registers and logging	2023-09-18 14:40:23 +02:00
TQ Hirsch	a1daa4c4b3	Fully implemented CPU and memory busses, but not yet tested	2023-08-31 13:46:28 +02:00