thequux/jdp11
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: thequux:d90304b5fd36b1d069a3cb7b25dc63238bd259df
Branches Tags
thequux:master
...
compare: thequux:master
Branches Tags
thequux:master

3 Commits
d90304b5fd ... master

Author SHA1 Message Date
TQ Hirsch
a155097903 Cleaned up order of writing condition codes and result of insns 2023-10-14 14:40:08 +02:00
TQ Hirsch
b512f1a42f Fixed DATO/flag ordering for MOV. Still needs to be done for the rest of the insns 2023-09-30 20:12:53 +02:00
TQ Hirsch
ef5d8d73c7 Provided docs for running diagnostics 2023-09-30 19:46:36 +02:00
4 changed files with 75 additions and 50 deletions
Expand all files Collapse all files

16
doc/diagnostics.md Normal file
View File

@@ -0,0 +1,16 @@
# Running ekba
This will run for a total of 541450515 instructions. To just run the first pass (132198 insns), break at 10742.
```
# Start address of 0200, no switch settings, break at end of second pass.
jdp11 -l diag/ekba.pt -g 200 -b 10722
```
# Running ekbb
This will run for around 1144728 instructions.
```
# Start address of 0200, switch set to 161 to disable unibus trap tests, break at 36170, which is the end of the test
jdp11 -l diag/ekbb.pt -g 200 -s 161 -b 36170
```

6
src/main/kotlin/com/thequux/mcpdp/Loader.kt
View File

@@ -65,13 +65,13 @@ fun CPU.loadAbs(infile: File) {
if (cksum != 0) {
throw Exception("Incorrect checksum: 0x${cksum.toString(16)}")
}
logger.debug("Loading 0x${len.toString(16)} bytes at 0x${addr.toString(16)}")
logger.trace("Loading 0x${len.toString(16)} bytes at 0x${addr.toString(16)}")
if (len == 0) {
// end of file
logger.debug("Tape ended at ${pos+len+7}")
logger.trace("Tape ended at ${pos+len+7}")
if (!(addr bit 0)){
this.pc = addr
logger.debug("Ready to run at ${addr.toString(8)}")
logger.trace("Ready to run at ${addr.toString(8)}")
}
return
} else {

101
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
View File

@@ -111,7 +111,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
registers[reg] = stack_pop()
} // RTS
in 0x98..0x9F -> {
if (cur_mode == 0) psw_priority = opcode and 0x7
if (cur_mode == 0) psw_priority_next = opcode and 0x7
} // SPL
in 0xA0..0xBF -> {
val flag = opcode bit 4
@@ -125,11 +125,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val dst = opc_dst(opcode)
val v = op_loadw(dst)
val res = (v shl 8) or (v shr 8)
op_storw(dst, res)
V = false
C = false
N = res bit 7
Z = (res and 0xFFu) == 0.toUShort()
op_storw(dst, res)
} // SWAB
else -> throw InvalidOpcodeException()
} }
@@ -154,35 +154,37 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
insnTable[0x0A] = {opcode ->
when (opcode shr 6 and 3) {
0 -> { // CLR
op_storw(opc_dst(opcode), 0U)
N = false
V = false
C = false
Z = true
op_storw(opc_dst(opcode), 0U)
} // CLR
1 -> { // COM
val dst = opc_dst(opcode)
val res = op_loadw(dst).inv().also { op_storw(dst, it) }
val res = op_loadw(dst).inv()
N = res bit 15
Z = res == 0U.toUShort()
C = true
V = false
op_storw(dst, res)
} // COM
2 -> { // INC
val dst = opc_dst(opcode)
val src = op_loadw(dst)
val res = src.inc()
op_storw(dst, res)
N = res bit 15
Z = res == 0.toUShort()
V = res == 0x8000.toUShort()
op_storw(dst, res)
} // INC
3 -> { // DEC
val dst = opc_dst(opcode)
val res = op_loadw(dst).dec().also { op_storw(dst, it) }
val res = op_loadw(dst).dec()
N = res bit 15
Z = res == 0.toUShort()
V = res == 0x7FFF.toUShort()
op_storw(dst, res)
} // DEC
}
} // CLR, COM, INC, DEC
@@ -191,31 +193,31 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
0 -> { // NEG
val dst = opc_dst(opcode)
val res = op_loadw(dst).inv().inc()
op_storw(dst, res)
N = res bit 15
Z = res == 0.toUShort()
V = res == 0x8000.toUShort()
C = !Z
op_storw(dst, res)
} // NEG
1 -> { // ADC
val dst = opc_dst(opcode)
val c: UShort = if (C) 1u else 0u
val res = (op_loadw(dst) + c).toUShort()
op_storw(dst, res)
N = res bit 15
Z = res == 0u.toUShort()
V = (res == 0x8000u.toUShort()) and C
C = Z and C
op_storw(dst, res)
} // ADC
2 -> {
val dst = opc_dst(opcode)
val src = op_loadw(dst)
val res = if (C) src.dec() else src
op_storw(dst, res)
N = res bit 15
Z = res == 0.toUShort()
V = res == 0x8000.toUShort()
C = C and (src == 0.toUShort())
op_storw(dst, res)
} // SBC
3 -> {
val dst = op_loadw(opc_dst(opcode))
@@ -232,41 +234,41 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val dst = opc_dst(opcode)
val src = op_loadw(dst)
val res = (src shr 1).bit(15, C)
op_storw(dst, res)
C = src bit 0
N = res bit 15
Z = res == 0.toUShort()
V = N xor C
op_storw(dst, res)
} // ROR
1 -> {
val dst = opc_dst(opcode)
val src = op_loadw(dst)
val res = (src shl 1).bit(0, C)
op_storw(dst, res)
C = src bit 15
N = res bit 15
Z = res == 0.toUShort()
V = N xor C
op_storw(dst, res)
} // ROL
2 -> { // ASR
val dst = opc_dst(opcode)
val src = op_loadw(dst).toShort()
val res = (src shr 1).toUShort()
op_storw(dst, res)
N = res bit 15
Z = res == 0.toUShort()
C = src bit 0
V = N xor C
op_storw(dst, res)
} // ASR
3 -> { // ASL
val dst = opc_dst(opcode)
val src = op_loadw(dst)
val res = src shl 1
op_storw(dst, res.toUShort())
N = res bit 15
Z = res == 0.toUShort()
C = src and 0x8000u != 0u.toUShort()
V = N xor C
op_storw(dst, res)
} // ASL
}
} // ROR, ROL, ASR, ASL
@@ -289,14 +291,17 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
// memory ref
core.getSpace(prv_mode).getw(src.toUShort(), dspace = false)
}
stack_push(v)
N = v bit 15
Z = v == 0u.toUShort()
V = false
stack_push(v)
} // MFPI // TODO
2 -> {
val v = stack_pop()
val dest = opc_dst(opcode)
N = v bit 15
Z = v == 0u.toUShort()
V = false
if (is_paddr_reg(dest)) {
if (dest and 7u == 6u && prv_mode != cur_mode) {
shadow_r6[prv_mode] = v
@@ -306,14 +311,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
// memory ref
core.getSpace(prv_mode).setw(dest.toUShort(), v, dspace = false)
}
N = v bit 15
Z = v == 0u.toUShort()
V = false
} // MTPI // TODO
3 -> {
op_storw(opc_dst(opcode), if (N) (-1).toUShort() else 0.toUShort())
Z = !N
V = false
op_storw(opc_dst(opcode), if (N) (-1).toUShort() else 0.toUShort())
} // SXT
}
} // MARK, MFPI, MTPI, SXT
@@ -325,10 +327,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val src = opc_src(opcode)
val dst = opc_dst(opcode)
op_loadw(src).also {
op_storw(dst, it)
N = it bit 15
Z = it == 0.toUShort()
V = false
op_storw(dst, it)
}
} // MOV
for (i in 0x20..0x2F) insnTable[i] = { opcode -> // CMP
@@ -352,19 +354,19 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val src = opc_src(opcode)
val dst = opc_dst(opcode)
val res = op_loadw(dst) and op_loadw(src).inv()
op_storw(dst, res)
N = res bit 15
Z = res == 0u.toUShort()
V = false
op_storw(dst, res)
} // BIC
for (i in 0x50..0x5F) insnTable[i] = { opcode -> // BIS
val src = opc_src(opcode)
val dst = opc_dst(opcode)
val res = op_loadw(dst) or op_loadw(src)
op_storw(dst, res)
N = res and 0x8000u != 0u.toUShort()
Z = res == 0u.toUShort()
V = false
op_storw(dst, res)
} // BIS
for (i in 0x60..0x6F) insnTable[i] = { opcode -> // ADD
val src = opc_src(opcode)
@@ -373,12 +375,12 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val dstv = op_loadw(dst)
val res = (srcv + dstv)
val resw = res.toUShort()
op_storw(dst, res.toUShort())
N = resw > 0x7FFFu
Z = resw == 0.toUShort()
val src_sign = srcv and 0x8000u
V = (src_sign == dstv and 0x8000u) && (src_sign != resw and 0x8000u)
C = (res >= 0x10000u)
op_storw(dst, res.toUShort())
} // ADD
insnTable[0x70] = { opcode -> // MUL
val r = opcode shr 6 and 0x7
@@ -493,10 +495,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val r = opcode shr 6 and 7
val dst = opc_dst(opcode)
val res = op_loadw(dst) xor registers[r]
op_storw(dst, res)
N = res bit 15
Z = res == 0.toUShort()
V = false
op_storw(dst, res)
} // XOR
// 0x7A and 0x7C are undefined
insnTable[0x7E] = { opcode -> // SOB
@@ -526,33 +528,36 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
insnTable[0x8A] = { opcode ->
when (opcode shr 6 and 3) {
0 -> { // CLRB
op_storb(opc_dstb(opcode), 0U)
N = false
V = false
C = false
Z = true
op_storb(opc_dstb(opcode), 0U)
} // CLRB
1 -> { // COMB
val dst = opc_dstb(opcode)
val res = op_loadb(dst).inv().also { op_storb(dst, it) }
val res = op_loadb(dst).inv()
N = res bit 7
Z = res == 0U.toUByte()
C = true
V = false
op_storb(dst, res)
} // COMB
2 -> { // INC
2 -> { // INCB
val dst = opc_dstb(opcode)
val res = op_loadb(dst).inc().also { op_storb(dst, it) }
val res = op_loadb(dst).inc()
N = res bit 7
Z = res == 0.toUByte()
V = res == 0x80.toUByte()
op_storb(dst, res)
} // INCB
3 -> { // DEC
val dst = opc_dstb(opcode)
val res = op_loadb(dst).dec().also { op_storb(dst, it) }
val res = op_loadb(dst).dec()
N = res bit 7
Z = res == 0.toUByte()
V = res == 0x7F.toUByte()
op_storb(dst, res)
} // DECB
}
} // CLRB, COMB, INCB, DECB
@@ -561,31 +566,31 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
0 -> { // NEGB
val dst = opc_dstb(opcode)
val res = op_loadb(dst).inv().inc()
op_storb(dst, res)
N = res bit 7
Z = res == 0.toUByte()
V = res == 0x8000.toUByte()
C = !Z
op_storb(dst, res)
} // NEGB
1 -> { // ADCB
val dst = opc_dstb(opcode)
val c: UShort = if (C) 1u else 0u
val res = (op_loadb(dst) + c).toUByte()
op_storb(dst, res)
N = res bit 7
Z = res == 0u.toUByte()
V = (res == 0x80u.toUByte()) and C
C = Z and C
op_storb(dst, res)
} // ADCB
2 -> {
val dst = opc_dstb(opcode)
val src = op_loadb(dst)
val res = if (C) src.dec() else src
op_storb(dst, res)
N = res bit 8
Z = res == 0.toUByte()
V = res == 0x80.toUByte()
C = C and (src == 0.toUByte())
op_storb(dst, res)
} // SBCB
3 -> {
val dst = op_loadb(opc_dstb(opcode))
@@ -602,41 +607,41 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val dst = opc_dstb(opcode)
val src = op_loadb(dst)
val res = (src shr 1).bit(7, C)
op_storb(dst, res)
C = src bit 0
N = res bit 7
Z = res == 0.toUByte()
V = N xor C
op_storb(dst, res)
} // RORB
1 -> {
val dst = opc_dstb(opcode)
val src = op_loadb(dst)
val res = (src shl 1).bit(0, C)
op_storb(dst, res)
C = src bit 7
N = res bit 7
Z = res == 0.toUByte()
V = N xor C
op_storb(dst, res)
} // ROLB
2 -> { // ASRB
val dst = opc_dstb(opcode)
val src = op_loadb(dst).toByte()
val res = (src shr 1).toUByte()
op_storb(dst, res)
N = res bit 7
Z = res == 0.toUByte()
C = src bit 0
V = N xor C
op_storb(dst, res)
} // ASRB
3 -> { // ASLB
val dst = opc_dstb(opcode)
val src = op_loadb(dst)
val res = (src shl 1).toUByte()
op_storw(dst, res.toUShort())
N = res bit 7
Z = res == 0.toUByte()
C = src bit 7
V = N xor C
op_storw(dst, res.toUShort())
} // ASLB
}
} // RORB, ROLB, ASRB, ASLB
@@ -653,14 +658,17 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
// memory ref
core.getSpace(prv_mode).getw(src.toUShort(), dspace = true)
}
stack_push(v)
N = v bit 15
Z = v == 0u.toUShort()
V = false
stack_push(v)
} // MFPD // TODO
2 -> {
val v = stack_pop()
val dest = opc_dst(opcode)
N = v bit 15
Z = v == 0u.toUShort()
V = false
if (is_paddr_reg(dest)) {
if (dest and 7u == 6u && prv_mode != cur_mode) {
shadow_r6[prv_mode] = v
@@ -670,9 +678,6 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
// memory ref
core.getSpace(prv_mode).setw(dest.toUShort(), v, dspace = true)
}
N = v bit 15
Z = v == 0u.toUShort()
V = false
} // MTPD // TODO
else -> { throw InvalidOpcodeException() } // Reserved
}
@@ -683,6 +688,9 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val dst = opc_dstb(opcode)
val dstv = op_loadb(src)
N = dstv bit 7
Z = dstv == 0.toUByte()
V = false
if (is_paddr_reg(dst)) {
op_storw(dst, dstv.toUShort() sex 8)
dstv.toUShort() sex 8
@@ -690,9 +698,6 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
op_storb(dst, dstv)
dstv.toUShort()
}
N = dstv bit 7
Z = dstv == 0.toUByte()
V = false
} // MOVB
for (i in 0xA0..0xAF) insnTable[i] = { opcode -> // CMPB
@@ -716,19 +721,19 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val src = opc_srcb(opcode)
val dst = opc_dstb(opcode)
val res = op_loadb(dst) and op_loadb(src).inv()
op_storb(dst, res)
N = res bit 7
Z = res == 0u.toUByte()
V = false
op_storb(dst, res)
} // BICB
for (i in 0xD0..0xDF) insnTable[i] = { opcode -> // BISB
val src = opc_srcb(opcode)
val dst = opc_dstb(opcode)
val res = op_loadb(dst) or op_loadb(src)
op_storb(dst, res)
N = res bit 7
Z = res == 0u.toUByte()
V = false
op_storb(dst, res)
} // BISB
for (i in 0xE0..0xEF) insnTable[i] = { opcode ->
val src = opc_src(opcode)
@@ -736,11 +741,11 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val srcv = op_loadw(src)
val dstv = op_loadw(dst)
val res = (dstv.toShort() - srcv.toShort())
op_storw(dst, res.toUShort())
N = res < 0
Z = res == 0
V = ((srcv bit 31) xor (dstv bit 15)) and ((srcv bit 15) == (res bit 31))
C = (dst.toInt() + src.inv().inc().toInt()) < 0x1_0000
op_storw(dst, res.toUShort())
} // SUB
// insnTable[0x0E] = // TODO: check this
// insnTable[0x0F] = // TODO: check this
@@ -796,7 +801,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
registerSet = newpsw shr 11 and 1
cur_mode = newpsw shr 14
prv_mode = newpsw shr 12 and 3
psw_priority = newpsw shr 5 and 7
psw_priority_next = newpsw shr 5 and 7
} else {
registerSet = registerSet or (newpsw shr 11 and 1)
cur_mode = cur_mode or (newpsw shr 14 and 3)
@@ -814,6 +819,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
}
private var prv_mode: Int = 0
private var psw_priority: Int = 0
private var psw_priority_next: Int = 0
var pc: UShort
get() = registers[7]
set(value) {
@@ -1122,8 +1128,10 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
}
if (runState == RunState.WAIT_FOR_INTERRUPT) {
// Note that it is impossible to have a pending priority change at the same time as a WAIT insn
return
}
psw_priority = psw_priority_next
// Proceed to handling instruction
try {
@@ -1188,6 +1196,7 @@ class CPU(val mbus: MemBus, var tracer: ITracer = NullTracer()) {
val old_psw = psw
val newPSW = core.getSpace(0).getw((vector + 2u).toUShort()) and 0xCFFFu or (cur_mode shl 12).toUShort()
setPSW(newPSW, true)
psw_priority = psw_priority_next // calling a vector sets priority immediately
stack_push(old_psw)
stack_push(pc)
pc = core.getw(vector)

2
src/main/kotlin/com/thequux/mcpdp/peripheral/DL11.kt
View File

@@ -42,7 +42,7 @@ class DL11(private var istr: InputStream, private val ostr: OutputStream, val re
override fun reset() {
rcsr = 0x0u
rcsr = 0x0u
// xcsr = 0x80u
xcsr = 0x80u
intrRcv.level = false
intrXmit.level = false