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Got another 40 insns into EKBA. Now at 247

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This commit is contained in:
TQ Hirsch
2023-09-19 23:11:06 +02:00
parent aee3672252
commit 82498e0c19
3 changed files with 33 additions and 18 deletions
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36
src/main/kotlin/com/thequux/mcpdp/core/CPU.kt
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@@ -7,7 +7,6 @@ import com.thequux.mcpdp.util.ProgrammerError
import org.slf4j.Logger
import org.slf4j.LoggerFactory
import java.lang.StringBuilder
import kotlin.math.log
/// The main CPU
///
@@ -607,8 +606,10 @@ class CPU(val mbus: MemBus) {
val dst = opc_dst(opcode)
val res = op_loadw(dst) and op_loadw(src)
N = res bit 15
Z = res != 0u.toUShort()
Z = res == 0u.toUShort()
V = false
logger.debug("RV: ${dst.toString(16)} RES: ${res.toString(16)}, SRC: ${op_loadw(src).toString(16)}")
debugFlags()
} // BIT
0x4000 -> { // BIC
val src = opc_src(opcode)
@@ -616,7 +617,7 @@ class CPU(val mbus: MemBus) {
val res = op_loadw(dst) and op_loadw(src).inv()
op_storw(dst, res)
N = res bit 15
Z = res != 0u.toUShort()
Z = res == 0u.toUShort()
V = false
} // BIC
0x5000 -> { // BIS
@@ -625,7 +626,7 @@ class CPU(val mbus: MemBus) {
val res = op_loadw(dst) or op_loadw(src)
op_storw(dst, res)
N = res and 0x8000u != 0u.toUShort()
Z = res != 0u.toUShort()
Z = res == 0u.toUShort()
V = false
} // BIS
0x6000 -> { // ADD
@@ -744,16 +745,21 @@ class CPU(val mbus: MemBus) {
0x9000 -> { // MOVB
val src = opc_srcb(opcode)
val dst = opc_dstb(opcode)
op_loadb(src).also {
if (dst bit 32) {
op_storw(dst, it.toUShort() sex 8)
} else {
op_storb(dst, it)
}
N = it bit 15
Z = it == 0.toUByte()
V = false
var dstv = op_loadb(src)
var dstw = if (is_paddr_reg(dst)) {
op_storw(dst, dstv.toUShort() sex 8)
dstv.toUShort() sex 8
} else {
op_storb(dst, dstv)
dstv.toUShort()
}
N = dstv bit 7
Z = dstv == 0.toUByte()
V = false
logger.debug("RV: ${dst.toString(16)} RES: ${dstw.toString(16)}, SRC: ${dstv.toString(16)}")
debugFlags()
} // MOVB
0xA000 -> { // CMPB
val src = op_loadb(opc_srcb(opcode))
@@ -778,7 +784,7 @@ class CPU(val mbus: MemBus) {
val res = op_loadb(dst) and op_loadb(src).inv()
op_storb(dst, res)
N = res bit 7
Z = res != 0u.toUByte()
Z = res == 0u.toUByte()
V = false
} // BICB
0xD000 -> { // BISB
@@ -787,7 +793,7 @@ class CPU(val mbus: MemBus) {
val res = op_loadb(dst) or op_loadb(src)
op_storb(dst, res)
N = res bit 7
Z = res != 0u.toUByte()
Z = res == 0u.toUByte()
V = false
} // BISB
0xE000 -> {

4
src/main/kotlin/com/thequux/mcpdp/ext/bit/bitext.kt
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@@ -46,8 +46,8 @@ inline fun UShort.bit(n: Int, v: Boolean): UShort = if (v) this bis n else this
inline infix fun UShort.bis(n: Int): UShort = this.toUInt().or(1U shl n).toUShort()
inline infix fun UShort.bic(n: Int): UShort = this.toUInt().and(1U.shl(n).inv()).toUShort()
inline infix fun UShort.sex(n: Int): UShort {
val sign = 1.toUShort() shl n+1
return ((this and sign.dec()) - (this and sign)).toUShort()
val sign = 1.toUShort() shl (n-1)
return (this - (this and sign shl 1)).toUShort()
}
inline fun UShort.maskSet(v: UShort, mask: UShort) = this and mask.inv() or (v and mask)

11
src/main/kotlin/com/thequux/mcpdp/util/DebugTools.kt
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@@ -116,8 +116,17 @@ class Disassembler(val core: VAddressSpace) {
in 0x40..0x7f -> fmt("JMP", dst()) // JMP
in 0x80..0x87 -> fmt("RTS", reg0()) // RTS
in 0x98..0x9F -> fmt("SPL", (opcode and 7).toString())
0xAF -> fmt("CCC")
in 0xA0..0xAE -> {
val items: ArrayList<String> = ArrayList()
if (opcode bit 0) items.add("CLC")
if (opcode bit 1) items.add("CLZ")
if (opcode bit 2) items.add("CLV")
if (opcode bit 3) items.add("CLN")
fmt(items.joinToString(" "))
} // Scc/Ccc
0xBF -> fmt("SCC")
in 0xA0..0xBE -> {
in 0xB0..0xBE -> {
val items: ArrayList<String> = ArrayList()
if (opcode bit 0) items.add("SEC")
if (opcode bit 1) items.add("SEZ")